Each of the revisions below represents a head commit in the pull request labeled with backend:SPIR-V in the LLVM repository.

• [SPIR-V] Implement support of the SPV_INTEL_split_barrier SPIRV …   QUEUED

  89a7d93d6e8e9e0769e3262376b8534a25903f66 10/15/2024 13:51

• [Clang][SYCL] Introduce clang-sycl-link-wrapper to link SYCL off…   QUEUED

  eff4a0300336c4c106e1d293b19e795f5ccbabc1 10/14/2024 19:03

• [Clang][SYCL] Introduce clang-sycl-link-wrapper to link SYCL off…   QUEUED

  753edc30b7fecba0085e8d9e9d03384e304d104f 10/14/2024 19:03

• [Clang][SYCL] Introduce clang-sycl-link-wrapper to link SYCL off…   QUEUED

  21a7b1c5f5ab7df002c5d4f941f0c6f1186bafe3 10/14/2024 19:03

• [Clang][SYCL] Introduce clang-sycl-link-wrapper to link SYCL off…   QUEUED

  e38ded01ae60cf50d295869c977308c1a8f620f3 10/14/2024 19:03

• [Clang][SYCL] Introduce clang-sycl-link-wrapper to link SYCL off…   QUEUED

  b78b2effd1e0a50cbcf51148a9246fcb9a38bfa1 10/14/2024 19:03

• [Clang][SYCL] Introduce clang-sycl-link-wrapper to link SYCL off…   QUEUED

  e69ddfdbd9e351cc040757197e3d921fb5757963 10/14/2024 19:03

• [SPIRV] Add GroupMemoryBarrierWithGroupSync intrinsic   QUEUED

  051ce26cbbbb4959bd06fcf7d2cbdc140923d6b5 10/10/2024 18:33

• [NFC][LLVM] Remove unused `TargetIntrinsicInfo` class   QUEUED

  36fa339d586b41f02bb431eb9af8665f6a82ea25 10/09/2024 21:10

• [NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclarat…   QUEUED

  b4e90932c73bff7ae0f1ac6ce6a0a0ab58f0a6e8 10/09/2024 19:37

• [SPIRV][HLSL] Handle arrays of resources   QUEUED

  9d80a7f096206b9a4e91ccd606682a8390ee199d 10/08/2024 17:23

• Overhaul the TargetMachine and LLVMTargetMachine Classes   QUEUED

  b52f940b385cabf51c96004a5d17e3bf0b1cd2e1 10/05/2024 06:08

• [HLSL] Implement the `degrees` intrinsic   QUEUED

  04fa155a8f45c2fdb30b9233f0bd7d4783045a55 10/04/2024 21:06

• [HLSL] Implement the `degrees` intrinsic   QUEUED

  461d5133ea1ae1fcdffd036a926243ee3dce5abb 10/04/2024 21:06

• [HLSL] Implement the `degrees` intrinsic   QUEUED

  398dcb5c1a354c12d4d43af152f6d3e14f001274 10/04/2024 21:06

• [HLSL] Implement the `degrees` intrinsic   QUEUED

  f7f55b9613775f4e77acf50b3a3ea13d09252c1f 10/04/2024 21:06

• [HLSL] Implement the `degrees` intrinsic   QUEUED

  b7a20c9a217400d44d5b84df771a4d47d5f89bba 10/04/2024 21:06

• [HLSL] Implement the `degrees` intrinsic   QUEUED

  7bd609f6017bc9389dfaa75b2aad9811e4981471 10/04/2024 21:06

• [SPIRV] Implement type deduction and reference to function decla…   QUEUED

  db9f3670e2759e18f6070930a237521db2b340c0 10/04/2024 13:55

• [HLSL] implement elementwise firstbithigh hlsl builtin   QUEUED

  122a18a81d74413173af4f47b1fd1c419d01d12b 10/04/2024 01:16

• [HLSL] implement elementwise firstbithigh hlsl builtin   QUEUED

  ff4093af55df1abff89f652957a0cdda543ff2ed 10/04/2024 01:16

• [HLSL] implement elementwise firstbithigh hlsl builtin   QUEUED

  7265e563e818325c982e3ed19247b9d383d6bb9e 10/04/2024 01:16

• [SPIRV] Implement handle_fromBinding intrinsic.   QUEUED

  8535758efac9d7bb90fd65f883f46dbdaa8e9aa5 10/03/2024 19:49

• [SPIRV] Implement handle_fromBinding intrinsic.   QUEUED

  6950fb9de452c37831ad7d12f30a5c1c8a1b6f2c 10/03/2024 19:49

• [SPIRV] Implement handle_fromBinding intrinsic.   QUEUED

  af91f0e29b0f26abe6814fea15aff96b796308d8 10/03/2024 19:49

• [SPIRV] Implement handle_fromBinding intrinsic.   QUEUED

  a0c5f9bdbf1bc7ea8d3cd34ede35c42ed5aac500 10/03/2024 19:49

• [SPIRV] Implement handle_fromBinding intrinsic.   QUEUED

  44a525bfe7526539fe1ae3291038d3bd041d1151 10/03/2024 19:49

• [HLSL] Implement `WaveReadLaneAt` intrinsic for spirv backend   QUEUED

  4522f35e2f9d0cc047b457851d28ebbc36e8038c 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic for spirv backend   QUEUED

  e8c5dba828f25c2894980631ae019936a3d9e9f6 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  1b0746f152b4eaa4f6e661787503fc6f7d1fdc72 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  5a2c5945ec293cd0d217e827b8e155b70e0af02b 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  32f10151be4a026672d7d04879c9907594a7c6a1 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  906f105f16080616ea84958e6e27761cd398e7b9 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  1fc05b6e910976d2e2f13f0690c3e227f161bc21 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  f181e2734298d96f92ecf00b817296115e4e7db0 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  49edfec7f8d2fb84144ef903bc5db3ab2099a1ae 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  466ae52a8124622a3763dea737a428d5cae6df67 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  78f7e5dfb7ee4e5650f1d1ecd0a6182a8f8dacb7 10/03/2024 15:59

• [HLSL] Implement `WaveReadLaneAt` intrinsic   QUEUED

  087191d23e61ef50c9c2b9648d10de8b9eb66171 10/03/2024 15:59

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  dc1a5f5d2e18b408fae3e04091dd653394695368 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  d5483cdc0d0133229b4d46bedd14dd7b5448d868 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  31a5ebe2248059c496043f234d994073f9066eb4 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  a01e1bc58fe6113d869d7d2d9889b1e8a1b26cfb 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  ab1fb667c81a32ca01a29b92095d21c464686615 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  168149a08c159ed4f7db7144f8ce8dc65219f77f 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  e1e57ad408a1215c6639db9c65c354ba2d21d034 10/02/2024 17:19

• [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for …   QUEUED

  102e8868523e606e9375498f7955a1a231294f0d 10/02/2024 17:19

• [NFC][SPIRV] Fix for selectExtInst to be able to process intrins…   QUEUED

  e3280d50b75e06963e80e8a52064113e1f37163c 10/02/2024 15:15

• [SPIRV] Make access qualifier optional for spirv.Image type   QUEUED

  d4f7f94810f3a88c09eddaa3513fc7c24a2e6561 10/02/2024 14:44

• [SPIRV] Make access qualifier optional for spirv.Image type   QUEUED

  17cbfc8a4947f5979449778bf0283700eaa305c2 10/02/2024 14:44

• [SPIR-V] Duplicates Tracker accounts for possible changes in Con…   QUEUED

  04b62315618c87d4a9240eddb7a0c7939c7a978d 10/02/2024 12:36

• [SPIRV] Add radians intrinsic   QUEUED

  1c6b14b94fc2f5835c4d57034a542978a404126d 10/02/2024 08:29

• [SPIRV] Add radians intrinsic   QUEUED

  735e8be18119af94cc9d3b307883c1edbdcf3737 10/02/2024 08:29

• [SPIRV] Add radians intrinsic   QUEUED

  0ab8d0fef887adda80e2d5367c937bdf3b4e8cfb 10/02/2024 08:29

• [SPIRV] Add radians intrinsic   QUEUED

  17175f2a298e243513e50e554cdddaaa87ace92a 10/02/2024 08:29

• [clang][llvm][SPIR-V] Explicitly encode native integer widths fo…   QUEUED

  758fb6e28844d89031b5497d651cb2a9b71b6a0e 10/01/2024 16:27

• [clang][llvm][SPIR-V] Explicitly encode native integer widths fo…   QUEUED

  f1c8446e81a461939e377e52f80f1c148ae4a286 10/01/2024 16:27

• [clang][llvm][SPIR-V] Explicitly encode native integer widths fo…   QUEUED

  9863f1d9079dafc279664609421c6f96b24d122c 10/01/2024 16:27

• [clang][llvm][SPIR-V] Explicitly encode native integer widths fo…   QUEUED

  c552d9919ddf679bc403a42888bd651a4ca97efe 10/01/2024 16:27

• [clang][llvm][SPIR-V] Explicitly encode native integer widths fo…   QUEUED

  04cdc23ec04f907afe8ae1bdaa4121d6d8712764 10/01/2024 16:27

• [SPIR-V] Support optimization of branching with analyzeBranch/re…   QUEUED

  40af699c755dc792c7ca99a9bebec93671fc4aa6 10/01/2024 12:05

• [SPIR-V] Support optimization of branching with analyzeBranch/re…   QUEUED

  633651abf3a34c83ad931b7ba968186139842238 10/01/2024 12:05

• [SPIR-V] Support optimization of branching with analyzeBranch/re…   QUEUED

  b43beb2c26e90c478da0d6d5335e0345084f2088 10/01/2024 12:05

• [MachineVerifier] Query TargetInstrInfo for PHI nodes.   QUEUED

  8d4cde5e9605c6ee5b80537b1947e0c92286ea66 09/30/2024 13:18

• [MachineVerifier] Query TargetInstrInfo for PHI nodes.   QUEUED

  8605d4d0dabe9219609fa24c1ebf4fcf45edb2a9 09/30/2024 13:18

• [MachineVerifier] Query TargetInstrInfo for PHI nodes.   QUEUED

  3fc31a5e6669b244a6bb2e6afd99e5eca8cc87d9 09/30/2024 13:18

• [SPIR-V] Implement support of the SPV_EXT_arithmetic_fence SPIRV…   QUEUED

  28f9d3e9a116663bb74ac57bdade0b5d7e18df6b 09/30/2024 12:30

• [SPIR-V][Codegen] Represent the property of the target to declar…   QUEUED

  70501ec2cc3167ed9f68061f5906bfaddc9c6993 09/27/2024 13:46

• [SPIR-V] Fix of OpString separator in DI test   QUEUED

  9bdb4134cf13d83038c46182c39365d8f9377291 09/27/2024 11:48

• [SPIR-V] Discard some llvm intrinsics which we do not expect to …   QUEUED

  4936b9881899d4a4221b1319a2ac5f95a64ca0b3 09/27/2024 10:08

• [SPIRV] Add atan2 function lowering (p2)   QUEUED

  e460be6d420238d9bcd1b69b20e5daadc4284872 09/25/2024 20:04

• [SPIRV] Add atan2 function lowering (p2)   QUEUED

  e2829371a1a9b95e46c238bc28acf909f4037372 09/25/2024 20:04

• [SPIR-V][Codegen] Add isPhi bit to MCInstrDesc/MIR definitions   QUEUED

  7334a2861bfc3a3b636a81000bb4f33daf221cf1 09/25/2024 17:58

• [SPIR-V] Implement OpSpecConstantOp with ptr-cast operation   QUEUED

  f0ed46e451337e9462f449ff65929c2a2653cb91 09/25/2024 13:34

• [SPIR-V] Implement OpSpecConstantOp with ptr-cast operation   QUEUED

  5fd4b0db82d928e190b4c920741cb6027df15844 09/25/2024 13:34

• [SPIR-V] Implement OpSpecConstantOp with ptr-cast operation   QUEUED

  0ab42b75e6d5febef3b6ab31e692f78e57e5acbc 09/25/2024 13:34

• [SPIR-V] Implement OpSpecConstantOp with ptr-cast operation   QUEUED

  d3325a25b70a4cebff18bb2a918db9a8a2f104b2 09/25/2024 13:34

• [SPIRV] Fix compilation error 'use of parameter from containing …   QUEUED

  de8acf86db6ea1254731bea8f3d516bad7821bdd 09/25/2024 08:13

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  eca4879a992d90b73c7d739ad48a75cb85fa064e 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  82a9f7292f14436cac2b53c841e6f707761c034a 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  25e9b3c3be185f605aed79a31c4525cf3a3c91a4 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  8597c6382dbbbed4a80f84156b80441c3fbfa339 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  fb29456295a449668860d09948792f5951395fff 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  75e39fa2687d4377085094197442036a050f8d73 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  4f6da8be459767ec6c05c38af49291abbf7e0f75 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  5476fcda96fd82b743aabe7de4f4f9eb49f1c28e 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  f0112ffe8fba129d0847d9afb548ef804dfa820a 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  f486701a3068f6741aae351b57b5abdd6dbd0589 09/24/2024 18:35

• [llvm][SPIRV] Expose fast `popcnt` support for SPIR-V targets   QUEUED

  178bc507e263161480ee1e00777f6c4522901934 09/24/2024 18:35

• [SPIR-V] Fix bad insertion for type/id MIR   QUEUED

  372611e186fc7eaea4f94c3ee7516d5d0e655dcd 09/23/2024 17:07

• [SPIR-V] Fix bad insertion for type/id MIR   QUEUED

  62c2c8a5fd066ab0787cad39e8f7d4f417e3c297 09/23/2024 17:07

• [SPIR-V] Fix inconsistency between previously deduced element ty…   QUEUED

  01c777628e17fce039f1b50297e6c2125445a255 09/23/2024 13:19

• [SPIR-V] Support for multiple DebugCompilationUnit in DI   QUEUED

  abf338e0fffdecc29d55439799c323f8a2798986 09/23/2024 10:16

• [SPIR-V] Support for multiple DebugCompilationUnit in DI   QUEUED

  08d90b1c4c675d196a66b7a65cd6e05c69eae4d7 09/23/2024 10:16

• [SPIR-V] Support for multiple DebugCompilationUnit in DI   QUEUED

  ad46e6e456fd43b57dfda9c28fa7e7567e40f5eb 09/23/2024 10:16

• [SPIR-V] Support for multiple DebugCompilationUnit in DI   QUEUED

  0b2a0c8cc11265efebca51670b476cc367ee7965 09/23/2024 10:16

• [SPIRV] Avoid repeated hash lookups (NFC)   QUEUED

  8bbd11db61c321ac070e269f8c25b60664fa83e6 09/21/2024 07:09

• [SPIR-V] Enable `spirv-sim` lit substitution unconditionally   QUEUED

  3a99576b575cb81138107147bdef160acc63db02 09/20/2024 17:56

• [SPIR-V] Fix deprecation warnings after #102608   QUEUED

  88a56cc78868d8961dc77bbd411de379ed6065f1 09/20/2024 17:33

• [SPIR-V] Fix minor build warnings   QUEUED

  37d36ecc13014771fcad3553c4869b7af768be62 09/20/2024 13:55

• [SPIR-V] Emit DebugTypePointer from NonSemantic DI   QUEUED

  ec9de0484fb1491cfbd9650bac09ce77f11ae2fe 09/19/2024 14:06

• [SPIR-V] Emit DebugTypePointer from NonSemantic DI   QUEUED

  80d33eb18b1fc55bccccfb02af79f0e4674bf592 09/19/2024 14:06

• [SPIR-V] Emit DebugTypePointer from NonSemantic DI   QUEUED

  428e06ef2c61a6eba8aedac200ef2113ef7254c8 09/19/2024 14:06

• [SPIR-V] Emit DebugTypePointer from NonSemantic DI   QUEUED

  91f36557066b0340d4dbe4c6be19c164473c4c35 09/19/2024 14:06

• [SPIR-V] Emit DebugTypePointer from NonSemantic DI   QUEUED

  811cea555bbb1b6e4d84c0ebf530a8e868e272a8 09/19/2024 14:06

• [SPIR-V] Emit DebugTypePointer from NonSemantic DI   QUEUED

  85ff63b6b0560531a25de12d803ab297d9f52262 09/19/2024 14:06

• [SPIRV] Avoid repeated hash lookups (NFC)   QUEUED

  b9a0bd1a305ed707a7401d8bcf4f7a129232f0fd 09/19/2024 06:20

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  3c58861f3e8c2f1333d0b36c6f5b7ba7f3d9e187 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  b5dc3e74bb9e2a347eb637f89b5c850af3d0ece4 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  a8f8faf343e5b21a74b7aa2fdc599a6aab2be28b 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  32d6add7b32535e5b1ba8fa428faf1cabde94b56 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  c13d2b1218044f01cc6dbc5d92da3335ecbc5fcf 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  f31ecc6d224c315cd86d6361c2a3ea8c5e90d118 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  81aa399533fa8d71b4f1508b27d03318981794ff 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  15defe2cc5a084e5600963fb803f9475b69263ec 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  8a367a5589e56e19d25af3440a688cd7489c1c3c 09/18/2024 19:21

• Add cross builtins and cross HLSL function to DirectX and SPIR-V…   QUEUED

  514c40bdffe65b1a153090da02cd2e90a981a3cf 09/18/2024 19:21

• [IR] Introduce `T<address space>` to `DataLayout` to repre…   QUEUED

  3052d9ab2225f32f0bed254f3d6eb64a096f3d5e 09/16/2024 02:45

• [IR] Introduce `T<address space>` to `DataLayout` to repre…   QUEUED

  cad9ac7478a158c455b8865cab8bb553a46f7773 09/16/2024 02:45

• [IR] Introduce `U<address space>` to `DataLayout` to repre…   QUEUED

  c2be824d5935b57a87a7ccf618ee4eecf55b4e3a 09/16/2024 02:45

• [SPIR-V] Fix incorrect emission of G_SPLAT_VECTOR for fixed vect…   QUEUED

  d78950daa5dadf9aa1d1587875539c7f4616868e 09/13/2024 11:12

• [SPIR-V] Align memory scopes with SPIR-V specification and LLVM …   QUEUED

  744d1c90710ef510d88d97918c716a71890025fc 09/13/2024 10:41

• [HLSL] Implement elementwise popcount   QUEUED

  365886deae6e35ee2761c2fae2a28caa0e214880 09/11/2024 00:31

• [HLSL] Implement elementwise popcount   QUEUED

  12b708d0d9e80c359756bc118579bd64439435e6 09/11/2024 00:31

• [HLSL] Implement elementwise popcount   QUEUED

  33880520ab83c51e526dddf057f049493bcbb4c2 09/11/2024 00:31

• [SPIR-V] Address the case when optimization uses GEP operator an…   QUEUED

  7f4644ebd1edcdd8c88caa1e9e4a20179da9db93 09/09/2024 15:52

• [SPIR-V] Address the case when optimization uses GEP operator an…   QUEUED

  533b61c8ccdf0906025c5042195ec8eeae9eb608 09/09/2024 15:52

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  edd878b8987d60efeef0aa2ff7fff76ee95c2a67 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  c913cfb3e81d5c31d9ce019fbe49210ad7ca45a0 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  75707219918fe1a0947ae851325c8f390d59a6af 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  949e0c5154987765796255b90ec524e79374577c 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  df2a2a072a010d757c23237afc9b7c721702fe2b 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  436d21dfeef434334935f3ec8fee269e415bc816 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  017395e61f6c952bd9b8a344b6a01fdb67d7d224 09/05/2024 14:38

• [SPIR-V] Add SPIR-V structurizer   QUEUED

  e00a2ba2f014c51f139462fb275cd61a5fb55c83 09/05/2024 14:38

• [SPIR-V] Expose an API call to initialize SPIRV target and trans…   QUEUED

  a11d3cea894a9be2bf7e3c357e9c70fc10743f7f 09/04/2024 10:51

• [SPIR-V] Expose an API call to initialize SPIRV target and trans…   QUEUED

  b2023ca443d49debc55b2b049a70adf35971cf53 09/04/2024 10:51

• [SPIR-V] Expose an API call to initialize SPIRV target and trans…   QUEUED

  d14d9faa099a9a220c41d63f01ed494a484c4ef2 09/04/2024 10:51

• [AsmPrinter] Do not emit label instructions after the function b…   QUEUED

  95eb6f4859decb56c79f25f5c77ea71a1c9f7547 09/02/2024 18:33

• [AsmPrinter] Do not emit label instructions after the function b…   QUEUED

  be842b5abd27a429d41b35981421f72c148170d4 09/02/2024 18:33

• [AsmPrinter] Do not emit label instructions after the function b…   QUEUED

  b61175c857633b7a7deef14b87491a2758f79b14 09/02/2024 18:33

• [SPIR-V] Ensure that OpExtInst instructions generated by NonSema…   QUEUED

  106c8a69d7fb4e00a48324dcc8fbfedaa4f66f10 09/02/2024 16:33

• [SPIR-V] Emit DebugTypeBasic for NonSemantic DI   QUEUED

  d943ea38c57fc41f3813d60ed46c2324e33380de 09/02/2024 12:42

• [SPIR-V] Emit DebugTypeBasic for NonSemantic DI   QUEUED

  d240f5a3aca1f26c51b2033cbbf3bd95ebb5b106 09/02/2024 12:42

• [SPIR-V] Emit DebugTypeBasic for NonSemantic DI   QUEUED

  c8598e925572439e8f51b619ad6661a8137e88a3 09/02/2024 12:42

• [SPIR-V] Emit DebugTypeBasic for NonSemantic DI   QUEUED

  ce8d085aefe8fc6940f298f03ddf159e4cef8dda 09/02/2024 12:42

• [SPIR-V] Emit DebugTypeBasic for NonSemantic DI   QUEUED

  4730439b50e0e74d5f7bba5270941de51ecf022c 09/02/2024 12:42

• [SPIR-V] Emit DebugTypeBasic for NonSemantic DI   QUEUED

  ee902a4324c81e2631b06a367654b3e40bf677b4 09/02/2024 12:42

• [SPIR-V] Improve correctness of emitted MIR between passes for b…   QUEUED

  b4df7434fefb7ef4fa081c5d17f00466359f034c 09/02/2024 10:11

• [SPIR-V] Improve correctness of emitted MIR between passes for b…   QUEUED

  93f447d2449bc421b80932cd0a609ab62b28f9b5 09/02/2024 10:11

• Add step builtins and step HLSL function to DirectX and SPIR-V b…   QUEUED

  7dfcf804ffcb850c7e3620866bc76f0971d82aaf 08/28/2024 23:37

• Add step builtins and step HLSL function to DirectX and SPIR-V b…   QUEUED

  7924bab45ce0436eb71a8548fe35f4d79594d00f 08/28/2024 23:37

• Add step builtins and step HLSL function to DirectX and SPIR-V b…   QUEUED

  13878a490f1f2f35a770ec9a6896f5d5c5294777 08/28/2024 23:37

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  25378a75752c134be0cef4999870819ba8ff8da1 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  b6fd508ab15c23f1dfd3497ed551c23448cd962d 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  79acf40bb2f053ab41728cf5d4ab514346254c69 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  bc712a3e0d7944c5fe1c60d723a0bfd818541f69 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  e984939b1c5364b9bf7b09f2282c5503752bddf4 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  8621e363c7987fefef4a72a945dc69a6cb94beac 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  9f87c0f46965cc2677ac59269c79bb15b1c2e376 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  e2f72fb162a0efc28e06cd208ae36c416dbc9e36 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  96a79e7c23d85097291c955bce65faf9b1ffde99 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  75776cc29b91ad5f58955fd03f6807f1f742f43d 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  92f739cb04f7b39f047c071d2e2c3d6f206dd231 08/28/2024 18:21

• [SPIRV][RFC] Rework / extend support for memory scopes   QUEUED

  2cb4b463a775c704a6c3499d60d24dda2c4bc589 08/28/2024 18:21

• [SPIR-V] Add definitions and fix implementation for atomic built…   QUEUED

  a1f5c192a07cb2689e909705da95968ef4e2ef7d 08/26/2024 17:16

• [SPIR-V] Add definitions and fix implementation for atomic built…   QUEUED

  8453c626b52598f9e7f9ce9fc5309c495c349371 08/26/2024 17:16

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  04b0bea4c4f6a0b576310f9fef697d07ea74d4ca 08/25/2024 21:53

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  217dcb414432f427295f86e5ca78f599ce8b9301 08/25/2024 21:53

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  15985f3e95a3dc50b2f4911392665cb5a79dfd96 08/25/2024 21:53

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  c8a49e1698cf579588e294cb910b507d24af7fa2 08/25/2024 21:53

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  af1d777f7e402b8a191a0e427130abca622113c0 08/25/2024 21:53

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  0b97772d037c4fdc61488190324e8d3896967438 08/25/2024 21:53

• [llvm] Consistently respect `naked` fn attribute in `TargetFrame…   QUEUED

  40941a587ce417a585437b4d1c4cba8ef02078b9 08/25/2024 21:53

• [SPIRV][test] Make debug info test robust to unix/windows differ…   QUEUED

  18df8e702adc3074ccf5957923597c37503b7617 08/25/2024 01:44

• [SPIRV] Fix return type mismatch for createSPIRVEmitNonSemanticD…   QUEUED

  cbc7dbbb80fe2c3049cb414535ce31adcad8d8e1 08/23/2024 21:07

• [SPIR-V][NFC] More efficient getPaddedLen   QUEUED

  48f55b5a3dbf3d04ec64eb9847f2e58a1340e35b 08/23/2024 12:41

• [SPIR-V] Fix vload_half builtin argument count   QUEUED

  03b7f794d1e710e0787142c4de050b302e0aba0d 08/21/2024 20:58